ROM redundancy in ROM embedded DRAM

ABSTRACT

Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or registers with ROM data which is read instead of erroneous data. Multiple identical arrays of ROM bits can also be used for redundancy.

RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.10/357,779, filed Feb. 4, 2003 now U.S. Pat. No. 7,174,477 and titled,“ROM REDUNDANCY IN ROM EMBEDDED DRAM,” which is commonly assigned andincorporated by reference in its entirety herein.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices, and morespecifically to a read only memory (ROM) embedded in a dynamic randomaccess memory (DRAM).

BACKGROUND

DRAM technology builds redundancy into DRAM arrays. Such redundancyallows for reassigning data storage to another redundantrow/column/block of a memory array to compensate for inevitable defectsin processing. Since modem DRAM arrays are so vastly large in number ofcells, and so vastly small in terms of actual size per cell, even smallerrors in processing can affect cells. By building redundancy into DRAMarrays, yield is improved since reprogramming of some portion of a DRAMarray is far superior to wasting the entire part due to a few smalldefects. Since the defect rate is actually not very large, a singleredundancy array is sufficient to compensate for most errors inprocessing of a modem DRAM array.

In redundancy in DRAM arrays, spare elements such as rows or columns areused as logical substitutes for a defective element or elements. Thesubstitution of redundant rows or columns for defective rows or columnsis controlled by a physical encoding scheme. As memory density and sizeincrease, redundancy becomes more and more important. Row and columnredundancy are commonplace in modem DRAMs. Further, some DRAMmanufacturers have begun to experiment with entire subarray redundancy.

Row redundancy replaces bad word lines with good word lines. Any numberof problems could exist on word lines, including shorted or open wordlines, word line to digit line shorts, bad transistors or storagecapacitors, and the like.

A ROM embedded DRAM is a DRAM array that has been modified slightly toallow for a portion of the DRAM array cells to be converted into ROMcells. Such a ROM embedded DRAM is described in greater detail in U.S.Pat. No. 6,134,137 issued Oct. 17, 2000 entitled “ROM-Embedded-DRAM”,incorporated herein by reference. U.S. Pat. No. 6,134,137 teaches thatslight modifications in fabrication masks allow DRAM cells to be hardprogrammed to V_(cc) or V_(ss) by shorting the cell to word lines. Thememory reads the ROM cells in a manner that is identical to reading theDRAM cells.

In a ROM embedded DRAM, problems with DRAM cells that have beenconverted to ROM cells can contribute to ROM defects. For example, if aDRAM cell on a portion of the ROM embedded DRAM is to be programmed byhard shorting to a 0 logic, but it is open and stuck at a 1 logic, therewould be an error.

In row redundancy, when a row address is strobed into a DRAM, theaddress is compared to a known bad address bank. If a bad address isrequested, a replacement word line is fired in place of the defective orbad word line. The replacement word line can appear anywhere on the DRAMarray. Repair of rows is termed either global or local. If thereplacement word line is in the same subarray as the bad word line, therepair is termed a local repair. If the bad word line is in a differentsubarray than the replacement word line, the repair is termed a globalrepair. Global repair is more desirable because the amount of repair islimited in each subarray. If one particular subarray has a large numberof defects, and all the repairs are local, the subarray could run out ofavailable replacement rows, and the entire chip becomes scrap. Globalrepair is very effective for cluster type failures, and is especiallyhelpful for larger DRAMs.

There are many different redundancy repair schemes, which are beyond thescope of this application, but which are readily known to those of skillin the art. For example only and not by way of limitation, repairschemes include antifuses, dynamic logic, and the like. Redundant wordlines are often capable of pretesting to determine whether they are goodor bad before actual selection of the replacement word line. This allowsfor selection of a good replacement word line and the concordant lack ofnecessity to change many replacement word lines to second replacementword lines.

Column redundancy schemes are also available on most modem DRAMs. Columnredundancy differs from row redundancy in that it is often the case thatcolumn addresses can be accessed multiple times per row address strobecycle. Each column is held open until a subsequent column appears.Typical column fuse blocks for column redundancy are built using staticlogic gates rather than dynamic logic gates. Dynamic gates require aprecharge and evaluation (P&E) and sufficient time to perform the P&Emay not be present with unpredictable column addressing. In some modemDRAMs, such P&E will work, and in that case, the schemes for columnredundancy are very close to that of row redundancy. However, in someother DRAM architectures, static redundancy is used.

It would be desirable to implement redundancy in the ROM portion of aROM embedded DRAM.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a ROM embedded DRAM on which embodiments ofthe present invention are practiced;

FIG. 2 is a block diagram of a ROM embedded DRAM according to oneembodiment of the present invention;

FIG. 3 is a block diagram of a ROM embedded DRAM according to anotherembodiment of the present invention; and

FIG. 4 is a flow chart diagram of a method according to one embodimentof the present invention.

DETAILED DESCRIPTION

In the following detailed description of the embodiments, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown by way of illustration specific embodiments in which theinvention may be practiced. It is to be understood that otherembodiments may be utilized and structural or logical changes may bemade without departing from the scope of the present invention.

The following detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

A ROM embedded DRAM is a DRAM array having a portion of the arrayutilized as a ROM array, and another portion of the array used as anormal DRAM array. Referring to FIG. 1, a simplified block diagram of aROM embedded DRAM 100 of the present invention is described. The memorydevice can be coupled to a processor 110 for bi-directional datacommunication. The memory includes an array of memory cells 112. Thearray includes a dynamic (DRAM) portion 120 and a read only (ROM)portion 122. The ROM array is “embedded” in the dynamic memory and mayinclude some dynamic cells. Control circuitry 124 is provided to managedata storage and retrieval from the array in response to control signals140 from the processor. Address circuitry 126, X-decoder 128 andY-decoder 130 analyze address signals 142 and storage access locationsof the array. Sense circuitry 132 is used to read data from the arrayand couple output data to I/O circuitry 134. The I/O circuitry operatesin a bi-directional manner to receive data from processor 110 and passthis data to array 112. It is noted that the sense circuitry may not beused in some embodiments to store the input data.

Dynamic memories are well known, and those skilled in the art willappreciate that the above-described ROM embedded DRAM has beensimplified to provide a basic understanding of DRAM technology and isnot intended to describe all of the features of a DRAM. The presentinvention uses the basic architecture and fabrication techniques of aDRAM and provides an embedded ROM array for non-volatile storage ofdata. This data can be used to store boot-type data for a system, anon-volatile look-up table, or other data that does not require adedicated ROM memory device. Embedding ROM storage in a DRAM is mosteconomically beneficial if the DRAM is not substantially altered duringfabrication or operation. That is, small fabrication changes allow theembedded memory to be fabricated using known techniques. Further, it isdesired to maintain operation of the memory in a manner that isexternally transparent. As such, an external processor, or system, doesnot need special protocol to interface with the embedded memory. Asdescribed below, the present invention provides an improved ROM embeddedDRAM having ROM portion redundancy.

ROM bits are hard programmed in a ROM embedded DRAM by any number ofprogramming techniques, including by way of example only and not by wayof limitation, hard programming by eliminating cell dielectric to shortcell plates to a program voltage, or by fabricating an electrical plugbetween the cell plates and shorted to a program voltage, programmingusing an anti-fuse programming technique, or by providing a high leakagepath (not full short) such as through an active area to the substrate.

There is an advantage in building in redundancy in a ROM when it isfabricated as a ROM embedded DRAM. Since there are so many possiblesmall defects that can crop up among the many millions of devices on atypical sized ROM embedded DRAM or DRAM chip, it is beneficial to allowfor some repair. Typically, this is done through redundancy. The repairembodiments of the present invention range from repair of everythingfrom a single bit up to an entire array.

Instead of testing to determine errors as in DRAM technology, it isnecessary to check to see if the ROM bit of the ROM embedded DRAMcontains data to which it has been programmed, that is either a 1 or a0, statically.

In order to accomplish this, several different embodiments are shown.Repairs on ROM embedded DRAM can be performed in the various embodimentson any number of bits from a single bit repair to an entire subarrayrepair.

A ROM embedded DRAM 200 having ROM portion redundancy is shown in oneembodiment in FIG. 2. The standard ROM embedded DRAM is modified in thisembodiment by adding a register or lookup table 202 which is capable ofbidirectional communication with the address circuitry and the ROM, andin another embodiment the processor. During programming of the ROMportion of the ROM embedded DRAM, the lookup table or other informationstorage array is generated. The lookup table contains row and addressinformation for each of the ROM bits in the ROM portion of the ROMembedded DRAM which is determined to be defective, and also contains thecorrect polarity, that is the value (1 or 0) that the defective ROM bitis supposed to hold.

Upon checking of the ROM portion after the programming of the ROMportion is completed, any ROM bits which are not properly programmed areidentified by row address and column address. The bad or defective rowand column addresses are stored in a register, bank of antifuses, or thelike, and when a row and address for reading is presented to the ROMportion of the ROM embedded DRAM via the address circuitry, the receivedaddresses are checked against the table, register, or bank of known badaddresses. If a match is found between the received addresses and thebad address lookup, the request for the data at the bad address isrerouted to the lookup table 202 containing the proper ROM bit for thereceived address. This ROM bit is read out as the requested ROM bit. Inone embodiment, the lookup table 202 includes not only the row, address,and polarity information, but also the bad row and address information.In another embodiment, the lookup table and the bad address register areseparate.

In operation, the lookup table or redundancy register contains all thenormal circuitry of a redundancy array, but also contains an extra bitto store correct ROM bit polarity. During testing, bad addresses aredetermined, and stored in the lookup table along with the correct ROMbit polarity that is supposed to be stored in the cell at the receivedrow and column address. The ROM bit is simply an extra bit which isprogrammed along with the row and column address when a particular ROMbit is determined during testing to be defective. Redundancy circuitryin another embodiment comprises a defective ROM bit address register anda defective ROM bit address bank.

The bits of such a redundancy compare circuit are typically programmedusing antifuses. When the address circuitry determines that a defectiverow and column address has been received, the address circuitry looks upthe address in the lookup table, and uses the programmed correctpolarity bit in the lookup table as the data to be read out from theROM. It should be understood that the size of the redundancy comparecircuit or lookup table can be varied without departing from the scopeof the invention. For example, the redundancy compare circuit or lookuptable is made larger in another embodiment. The only factor limitingsize of the redundancy compare circuit or lookup table is real estateavailable.

Various redundancy schemes are appropriate for the rerouting of badaddresses once the bad addresses are known. The provision in a lookuptable such as lookup table 202 of the appropriate ROM bits allowsredundancy in the live array ROM portion of the ROM embedded DRAMwithout the need for actually having redundant cells. Instead, the tablecontains the pertinent correct ROM bit information, which is read outwhen there is an error or defect in the live array ROM portion of theROM embedded DRAM. In an alternative embodiment, correcting the ROM bitdata is accomplished by inverting the read ROM bit polarity for a knowndefective ROM bit prior to sending the data to an output pin of thememory device.

In another embodiment, only ROM bits which are to be hard shorted to aspecific polarity are checked, with the remaining ROM bits assumed byaddress to be the opposite polarity. In other words, the ROM portion ofthe ROM embedded DRAM is programmed so that all of the bits to be hardshorted to a certain polarity, say 0, are hard shorted to zero logic,and then checked to see if any errors occurred on those bits. Theremaining ROM bits of the ROM embedded DRAM, namely those bits which areto be 1 polarity bits, are assumed by software, hardware, or firmware tobe 1 bits. This reduces the size of the lookup table needed for the ROMportion of the ROM embedded DRAM, but may increase the complexity ofsoftware, hardware or firmware used in decoding the ROM bits.

In another embodiment, a ROM embedded DRAM array has an array ofantifuses that are used for redundancy in the array as described above.Upon testing in a DRAM, for example, if a row or column of the DRAM isfound to be bad, that row or column is routed to a redundant set ofelements for execution of the memory storage desired. This is done, asdescribed above, by programming antifuses or the like to replace adesignated row address with a new destination row address. In oneembodiment of the present invention, an array of antifuses is usedsimilarly to the use in a typical DRAM. However, in the case of a ROMembedded DRAM, the necessary information for each bit includes not onlya row and a column address, but also a polarity of the ROM bit to bedecoded. In other words, each ROM bit is identified by a row address anda column address, and also by a polarity of the ROM bit, that is a 1 ora 0 value. This information is stored in a register or the like so as tobe readily available when a bad row and column address is received.

On a ROM embedded DRAM, a test is run to check the encoding of the ROMsection. When testing is complete, the necessary rerouting of rows,columns, bits and the like is known, and is then performed. This isaccomplished in various embodiments following typical DRAM redundancyreprogramming for defective rows and columns or addresses, with theadded process of encoding or pointing to information pertaining to thesections containing the correct ROM data as well as the row and columnaddress of the ROM bit.

In a normal DRAM, the programming of an antifuse leads to the reroutingof a row or column to a redundant row or column of memory bits. In thisembodiment, it is not necessary to reroute to a redundant column or rowof memory bits. Instead, what is done by blowing the antifuse in anantifuse redundancy scheme is to reroute to a lookup table, register,bank of antifuses, or the like, such as lookup table 202, that isprogrammed to look up or is encoded with the row and column address ofthe ROM bits, as well as the polarity of the ROM bits.

In one embodiment, the lookup is made in a bank of antifuses. The bankof antifuses has a register, wherein each of the antifuses correspondsto a particular row and column address, and is registered at each rowand column address, that is at each and every defective ROM bit, withthe polarity of the specific ROM bit that matches the row and columnaddress that is desired to be accessed.

In this embodiment, the ROM has been described as if it were programmedat a manufacturing facility, that is not field programmed. For example,a mask for making the ROM is coded with the desired ROM hard wiringinformation, and is encoded in the manufacturing process. Once the ROMis encoded, it is tested. If errors occur, they are repaired using oneof the redundancy techniques discussed above. The repair is performed inone embodiment by blowing the antifuse in the redundancy part of the ROMthat corresponds to the bit which has an error so that it readscorrectly.

In this embodiment, the ROM has been discussed with hard coded ROMprogramming, that is programming done at the manufacturing location.However, it should be understood that field programmable ROMs (PROMs)are used in another embodiment. In that embodiment, the field programmerfield programs a ROM as PROMs are typically programmed. Then, testing isperformed. At that point, the customer or field programmer must know theredundancy scheme in order to effect repairs on the ROM embedded DRAMROM portion.

In another embodiment 300 shown in block diagram in FIG. 3, twoidentical banks of ROM embedded DRAM ROM cells 302 and 304 are created.At the time of programming, each ROM bit is programmed to each array,primary array 302 and secondary array 304, and to a redundancy comparecircuit 306, with its polarity and row and address location. Upontesting, the row and address are determined, and the value in the memorycell at the received row and address is compared to the value of thepolarity stored in the redundancy compare circuit. If the actual bitvalue in addressed location of the primary array 302 does not match thestored bit value, then the row and address are redundantly programmed tolook up the same row and address in the redundant or secondary array304. Only if each of the arrays 302 and 304 contains an identical biterror will a problem arise.

The redundancy scheme of FIG. 3 allows for the repair of errors from asingle bit up to and including an entire array, provided the errors inthe arrays do not overlap. For example, each of arrays 302 and 304 areencoded with the same ROM bit mask in a ROM embedded DRAM programming.At the time of programming, the redundancy compare circuit 306 is alsoencoded or programmed with the row and address information and ROM bitpolarity of each of the ROM bits in the arrays. Arrays 302 and 304 areidentical without errors. A received address indicates the location ofthe ROM bit 308 of array 302 whose value is desired to be read. Thevalue read out from the cell 308 is compared in the redundancy comparecircuit to the desired value. If the values match, the data is read outof cell 308 to the data out and operation continues as normal. If on theother hand, the values do not match, the redundancy compare circuitpoints the particular received row and address to the secondary array304 cell 310 which is masked to be programmed identically to cell 308 ofarray 302. If the value on the redundancy compare circuit and thesecondary array match, the value of cell 310 is read out of cell 310 andoperation continues as normal.

In this manner, individual bit errors are repaired in redundant arrayfashion. It should be seen that not only are individual bit errorsrepairable using the redundancy configuration of FIG. 3, but also biterrors on a larger scale are repairable. For example, the arrays 302 and304 are in another embodiment subdivided into smaller subarrays. Iferrors occur in a subarray of the primary ROM embedded DRAM ROM array302, the bad subarray addresses are pointed to corresponding subarraylocations of the secondary array 304. Repair schemes according to thisembodiment are amenable to repair of rows, columns, individual bits,blocks, and the like.

In another example of operation of such a redundancy configuration, theROM embedded DRAM 300 has enough memory bits to make at least two imagesof a desired ROM portion of the ROM embedded DRAM. For example, acustomer desires 64 MB of DRAM and 32 MB of ROM on the same chip. Inthis instance, a 128 MB ROM embedded DRAM can be programmed to have 64MB of DRAM, and two arrays of 32 MB of ROM. Each of the two arrays ofROM in this embodiment are identical images of one another. The ROMsections are programmed with the desired information that the customerwishes to have programmed in the ROM section. Then, once the programmingis performed, the ROM arrays are tested to determine if any errorsexist. If an error is found in the primary ROM section, the bad section,be it a single bit, a row, a column, a subarray, a block, or even theentire array, is mapped to the secondary array. Identification of badbits, segments, and the like is accomplished in various ways, forexample only and not by way of limitation, using fuse banks, antifusebanks, or registers. When blown, an antifuse reroutes a specific row andcolumn location, or an entire subarray or the like, of the primary ROMarray to the same location on the secondary ROM array.

In yet another embodiment, blocks of any size from an individual bit onup to an entire ROM section of a ROM embedded DRAM are redundantlyrepairable. If ever increasing amounts of reliability are required, thenumber of redundant blocks is in other embodiments increased. Forexample, in a 256 MB DRAM chip, perhaps the customer only wishes to have64 MB of RAM, and the rest of the chip is available for ROM embedded inthe DRAM, then 192 MB is available for ROM. In many cases, the amount ofROM desired is actually quite low, for example 32 MB. In this instance,six 32 MB arrays are formed to allow for greatly increased multipleredundancy for the ROM portion of the ROM embedded DRAM. It should beseen that the actual configuration of the amount of redundancy will varydepending upon the desired yield of DRAM versus ROM for the ROM embeddedDRAM, and for the level of redundancy desired in the configuration.

In another embodiment, a combination of other embodiments comprisesfirst and second identical arrays as in FIG. 3, and further redundancyon the second array as in FIG. 2. Such a configuration, for its limitedvalue, is less desirable since the extra logic and space allowed aregenerally more useful in other endeavors.

However, in a situation in which there is enough room for redundancy butnot enough for an entire second array, such a combination provides anextra measure of reparability to the chip. For example, if a ROMembedded DRAM chip has enough room for the customer's desired DRAM/ROMconfiguration, with enough leftover room for a redundant ROM arrayimage, and for a redundancy scheme of antifuses for one of the ROMsubarrays but not both, such a combination provides extra reparabilitywithout sacrificing usability.

In another embodiment, testing of the ROM portion of the ROM embeddedDRAM identifies the predominant type of error in the ROM portion of theROM embedded DRAM. The redundant array is broken into segments or chunksaccording to the predominant type of error. For example, if thepredominant error type is single bit errors, the redundant array issubdivided into individual bits. If the predominant error type isblocks, the redundant array is subdivided into blocks of a determinedsize, and reprogramming is of blocks instead of individual bits.

In yet another embodiment, the specific fabrication process may lenditself to have predominantly a specific type of error. A redundant ROMarray is divided in this embodiment into subarrays according to thelikely type of errors. Software built into ROM programming in anotherembodiment allows the redundant array to be subdivided after testingaccording to a predominant type of error found during testing.

A ROM embedded DRAM having a section of ROM programmed bits and asection of DRAM bits is advantageously used in certain situations inwhich non-volatile memory is desired or required, but where speed isalso a factor. In such a situation, a ROM embedded DRAM has the contentsof the ROM section read into RAM on startup or trigger. The ROM portionis then no longer needed, as all operations are performed using the ROMcopied into RAM. That is, a ROM to RAM copy, allowing the ROM to bemodified while maintaining the integrity of the ROM encoding for lateruse. Such an embodiment is especially useful in situations where the ROMread is a long process, or the ROM consumes more power than is desiredto be consumed if read multiple times. Such an embodiment is useful inconfigurations where real estate is a primary concern. In suchsituations, a single chip having both ROM and DRAM sections is employed,thereby using only one chip instead of the usual two chips. For example,hearing aids, cellular telephones, and other size constrainedapparatuses, are amenable to the embodiments of the present invention.

In yet another embodiment, ROM embedded in DRAM is read into RAM onstartup to allow for faster operation of the ROM portion of the DRAM.For example, it may be desirable in one embodiment to program certainstartup options which will always remain the same into ROM. However, ROMtypically runs slower than RAM. In this instance, during startup, thecontents of the ROM portion of the ROM embedded DRAM are read into RAMso that they can be executed with greater speed. This also allows forthe possibility of changing the ROM parameters temporarily, knowing thatupon another restart, the original ROM encoding will again be available.

A method 400 of redundancy testing in a ROM embedded DRAM is shown inflow chart diagram in FIG. 4. Method 400 comprises programming the ROMportion of the ROM embedded DRAM in block 402, and testing the ROMportion of the ROM embedded DRAM to identify errors in the ROM portionin block 404. If errors are detected, they are corrected in block 406.The fixing of errors is accomplished in one of numerous ways asdescribed above in the various embodiments. For example only, and not byway of limitation, the ROM errors are corrected by identifying bad rowand column addresses, and rerouting ROM reads to a lookup table for badaddresses, the lookup table, such as lookup table 202 as describedabove, containing not only the row and column address, but also thepolarity for each ROM bit, programming an antifuse array for redundancy,and rerouting bad addresses to an entirely different but identicallyprogrammed array. Redundancy configurations of this type allow therepair of individual bits on up to an entire ROM embedded DRAM ROMsection.

It is to be understood that the above description is intended to beillustrative, and not restrictive. Many other embodiments will beapparent to those of skill in the art upon reading and understanding theabove description. The scope of the invention should, therefore, bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

1. A ROM embedded DRAM, comprising: a memory array having a firstportion of ROM bits and a second portion of DRAM bits; a single storageelement containing row and column addresses of each defective ROM bitand of each correct ROM bit polarity data for each defective ROM bit;compare circuitry to compare the address of each ROM bit data with itscorresponding storage element data; and a redundancy compare circuit toredirect incorrect ROM bit data to the storage element data thatcontains correct ROM bit polarity data for that ROM bit.
 2. The ROMembedded DRAM of claim 1, wherein the storage element is a bank ofantifuses.
 3. A ROM embedded DRAM comprising: a ROM embedded DRAM arrayhaving a ROM portion and a DRAM portion; wherein the ROM portioncomprises first and second identical ROM bit subarrays; a single storageelement, the single storage element to store each of a defective ROM bitcolumn address, a defective ROM bit row address, and a correct polaritydata for each ROM bit; and a redundancy element to point to the secondsubarray containing correct polarity data if a predetermined portion ofthe first subarray is defective.
 4. The ROM embedded DRAM of claim 3,wherein the predetermined portion is an individual bit.
 5. The ROMembedded DRAM of claim 3, wherein the predetermined portion is a row. 6.The ROM embedded DRAM of claim 3, wherein the predetermined portion is acolumn.
 7. The ROM embedded DRAM of claim 3, wherein the predeterminedportion is a block.
 8. A method of repairing ROM bit errors in a ROMembedded DRAM, comprising: storing defective ROM bit row and columnaddress and correct ROM bit polarity data for each defective ROM bitinto a single redundancy storage element; determining whether a livearray ROM bit data is correct; and correcting the live array ROM bitdata if the live array ROM bit data and the redundancy stored data aredifferent.
 9. The method of claim 8, wherein determining whether the ROMbit data is correct comprises comparing its data to the storage elementdata.
 10. The method of claim 8, wherein correcting the ROM bit datacomprises inverting the read ROM bit polarity prior to sending the datato an output pin.
 11. The method of claim 8, wherein correcting the ROMbit data comprises providing the storage element ROM polarity instead ofthe ROM bit polarity in a read operation.
 12. The method of claim 8,wherein storing further comprises storing row and column addresses ofdetermined defective ROM bits.
 13. The method of claim 12, whereincorrecting comprises providing the storage element ROM polarity when adetermined defective row and column address combination is received. 14.A method of operating a ROM embedded DRAM, comprising: providing astorage element for bi-directional communication with address circuitryof a ROM portion of a ROM embedded DRAM; generating row and columnaddress information and correct bit polarity for each defective ROM bitin the ROM portion during programming of the ROM portion; storing therow and column information and correct bit polarity for each defectiveROM bit in the storage element; comparing a received address with thestorage element row and column information; and outputting the correctbit polarity from the storage element for addresses found in theregister.
 15. The method of claim 14, wherein storing is done in aregister.
 16. The method of claim 14, wherein storing is done in alookup table.
 17. A method of programming a ROM embedded DRAM,comprising: programming each ROM bit into each of a primary ROM arrayand a secondary ROM array of the ROM embedded DRAM; and programming eachROM bit with its polarity and row and address location into a redundancycompare circuit.
 18. The method of claim 17, and further comprising:comparing a value in a memory cell of the primary array with itscorresponding value in the redundancy compare circuit; programming therow and address redundantly to the secondary array when the bit value ofthe primary array and the bit value of the redundancy compare circuit donot match; and programming the row and address to a lookup table of theredundancy compare circuit when the bit value or each of the primaryarray and the secondary array and the bit value of the redundancycompare circuit do not match.
 19. A processing system, comprising: aprocessor; and a read only memory (ROM) embedded dynamic random accessmemory (DRAM) coupled to the processor to store data provided by theprocessor and to provide data to the processor, the memory comprising: aROM array and a DRAM array; address circuitry for addressing the ROMarray; and a redundancy compare circuit operatively connected to allowredundancy in the ROM array, the redundancy compare circuit comprising:a defective ROM bit address register that stores the row and columnaddress of each defective ROM bit; and a defective ROM bit address databank that stores the correct bit polarity of each defective ROM bit,wherein the defective ROM bit address data bank comprises a plurality ofantifuse bits, each antifuse bit corresponding to a polarity of a ROMbit with a row and column address identified as defective.
 20. Aprocessing system, comprising: a processor; and a read only memory (ROM)embedded dynamic random access memory (DRAM) coupled to the processor tostore data provided by the processor and to provide data to theprocessor, the memory comprising: a memory array having a first portionof ROM bits and a second portion of DRAM bits; a single storage elementcontaining row and column addresses of each defective ROM bit and ofeach correct ROM bit polarity data for each defective ROM bit; comparecircuitry to compare the address of each ROM bit data with itscorresponding storage element data; and a redundancy compare circuit toredirect incorrect ROM bit data to the storage element data thatcontains correct ROM bit polarity data for that ROM bit.
 21. Aprocessing system, comprising: a processor; and a read only memory (ROM)embedded dynamic random access memory (DRAM) coupled to the processor tostore data provided by the processor and to provide data to theprocessor, the memory comprising: a ROM array and a DRAM array; addresscircuitry for addressing the ROM array; and a redundancy compare circuitoperatively connected to allow redundancy in the ROM array, theredundancy compare circuit comprising: a defective ROM bit addressregister that stores the row and column address of each defective ROMbit; and a defective ROM bit address data bank that stores the correctbit polarity of each defective ROM bit correlated to the addressregister data for each ROM bit.